The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight and high efficiency. For example, SMPSs are widely used in personal computers and portable electronic devices such as cell phones. An SMPS achieves these advantages by switching a switching element such as a power MOSFET at a high frequency (usually tens to hundreds of kHz), with the frequency or duty cycle of the switching being adjusted using a feedback signal to convert an input voltage to a desired output voltage.
An SMPS may take the form of a rectifier (AC/DC converter), a DC/DC converter, a frequency changer (AC/AC) or an inverter (DC/AC).
In most SMPS topologies, the output voltage, Vout, is directly proportional to the input voltage, Vin:Vout∝DVin  Equation 1
In Equation 1 above, D is the duty cycle of the switching.
To minimise the difference between the actual output voltage and the desired output voltage, the duty cycle is usually controlled in dependence upon a feedback signal, wherein the feedback signal is an error signal between a measured output voltage and a desired output voltage. The error signal is fed back to a feedback unit that controls the duty cycle so that the measured output voltage is adjusted to the desired output voltage.
It is preferable for the output voltage of the SMPS to remain at its desired level under all conditions. However, transients on the input voltage will cause the output voltage to change almost immediately.
Typically, only the inertia in an output filter of the SMPS will decrease this effect. In addition the error signal fed back to the feedback unit is often too slow in changing the duty cycle, which introduces a large transient on the output voltage.
A known solution to the problems caused by input transients is to cascade a voltage feedforward (VFF) compensator 102 with a feedback unit 101 as shown in FIG. 1.
In the cascade, or series, arrangement shown in FIG. 1, the feedback unit 101 calculates a duty cycle for an SMPS (not shown in FIG. 1). The VFF compensator 102, which is separate from the feedback unit, calculates and applies VFF compensation to adjust the duty cycle that has already been calculated by the feedback unit 101.
Known feedforward systems based on the arrangement of FIG. 1 are disclosed in:    Calderone, L. Pinola, V. Varoli, □Optimal feed-forward compensation for PWM DC/DC converters with □linear□ and □quadratic□ conversion ratio, IEEE trans, Power Electron., vol. 7, No. 2, pp 349-355, April 1992.    B. Arbetter and D. Marksimovic, □Feedforward Pulse Width Modulators for Switching Power Converters,□ IEEE trans, Power Electron., vol. 12, no. 2, pp 361-368, March 1997.    M. K. Kazimierczuk, A. J. Edstron, □Open-loop peak voltage feedforward control of PWM Buck converter□ IEEE trans. Circuits and Systems I, vol. 47, No. 5, pp. 740-746, May 2000.    J.-P. Sjoroos, T. Suntio, J. Kyyra, K. Kostov, □Dynamic performance of buck converter with input voltage feedforward control,□ European Conference on Power Electronics and Applications, 2005.
An SMPS controlled by a digital control unit is shown in FIG. 2.
The input and output voltages of the SMPS 201 are sampled and converted to digital samples by analogue-to-digital converters (ADCs) 202 and 203.
Logic units 204 and 205 are used for transforming the samples to a form suitable for processing by the digital control unit and for noise filtering.
The output voltage samples from logic unit 205 are fed to the feedback unit 206, which applies a control law as explained below.
A typical control law for controlling the duty cycle of an SMPS is a proportional-integral-difference (PID), also referred to as proportional-integral-differential or proportional-integral-derivative, control law. Implementations of a feedback unit that apply a PID control law are shown in FIGS. 3A and 3B.
In both FIGS. 3A and 3B, X(n) is an error signal, representing the difference between a desired and an actual signal, wherein the signals are typically sampled values of a measured voltage. Y(n) is a correction signal calculated in dependence upon the error signal.
As can be seen from in FIG. 3A, X(n) is split into three signals.
The first signal is split and one part of the split signal is delayed by delay element 301. The delayed part of the signal is subtracted from the non-delayed part to generate a difference signal that is input to amplifier 305.
The second signal is a proportional signal and is input to amplifier 306.
The third signal is input to adder 302. The output from adder 302 is split and one part of the split signal is delayed by delay element 304. The delayed part of the signal is input to adder 302. The non-delayed part is an integral signal and is input to amplifier 307.
Proportional, integral and difference signals are therefore generated.
Generally speaking, the proportional signal determines the reaction to the current error signal, the integral signal determines the reaction based on the sum of recent error signal values (i.e. recent samples of the error signal) and the difference signal determines the reaction based on the rate at which the error signal is changing.
The proportional, integral and difference signals fed into amplifiers, or multipliers, 305, 306 and 307, are weighted by their respective gains of KD, KP and KI. The outputs of amplifiers 305, 306 and 307 are input to adder 308. The output of adder 308, which comprises a summation of the input signals to adder 308, is the control signal generated according to the PID control law.
The gains KP, KI and KD determine the response of the feedback unit and are set according to system requirements (such as response time to an error or extent of overshoot, for example).
A PID circuit with simplified hardware is shown in FIG. 3B.
In the PID implementation in FIG. 3B, the input signal X(n) is split and one part of it is input to amplifier, or multiplier, 311. The other part of is input to delay element 309.
The output of delay element 309 is split and one part of it is input to amplifier, or multiplier, 312. The other part of the output of delay element 309 is input to delay element 310. The output of delay element 310 is input to amplifier, or multiplier, 313.
The outputs of amplifiers, or multipliers, 311, 312 and 313 are input to the adder 314. The output of the adder 314 is split and one part of the split signal is output as the control signal. The other part of the slit signal is fed to delay element 315. The output of delay element 315 is input to the adder 314.
For the circuit design in FIG. 3B to correspond to that in FIG. 3A, the gains KA, KB and KC are calculated as:KA=KI+KP+KD  Equation 2KB=(KP+2KD)  Equation 3KC=KD  Equation 4
In the circuit of FIG. 3B, there is a feedback loop between the output of the adder 314 and an input to the adder. The feedback signal input to the adder typically is referred to as the integral signal and it is input to the integral input of the adder. A feedback unit with such an input to the adder is said to comprise an integrator.
The above PID control law is described, for example, in M. A. Alexander, D. E. Heineman, K. W. Fernald, S. K. Herrington, □Hardware efficient digital control loop architecture for a power converter,□ U.S. Pat. No. 7,239,257 B1 (Jul. 3, 2007).
In the feedback unit of FIG. 3B, the inputs to the adder 314 are weighted by constant factors (i.e. KA, KB and KC are constant; and the output of delay element 315 is weighted by the constant one). The circuit implementation is therefore an example of a direct form 1 implementation of a digital filter of order 2. Direct form 2 and transposed direct designs of feedback unit are also possible.
It will therefore be appreciated that the above-described PID control law is just one example of a suitable control law for determining the duty cycle of a SMPS. Many alternative control laws are also possible, such as PI, PD, P, I and FIR for example.
Referring again to FIG. 2, the output from the feedback unit 206 is adjusted by the VFF compensator 207, in dependence upon the input voltage samples from the logic unit 204, to produce a compensated duty cycle control signal.
The VFF compensation reduces the effects of transients on the input voltage so that the output voltage of the SMPS 201 is almost independent of the input voltage.
The compensated duty cycle control signal D is output from the digital control unit and is fed to a digital pulse width modulator 208. The digital pulse width modulator 208 translates the duty cycle control signal from a digital format to a pulse width modulated (PWM) duty cycle signal. The PWM signal is then output to control the switching elements of the SMPS 201.
The conditions for voltage feed forward compensation are explained below.
In a buck converter, the ideal duty cycle, D, is equal to:
                    D        =                              V            out                                V            in                                              Equation        ⁢                                  ⁢        5            
When the input voltage changes, from Vin-old to Vin-new, the old duty cycle, Dold, should be scaled to a new duty cycle, Dnew, so the output voltage remains constant.
                                                                        V                out                            =                            ⁢                                                D                  old                                ⁢                                  V                                      in                    -                    old                                                                                                                          =                            ⁢                                                D                  new                                ⁢                                  V                                      in                    -                    new                                                                                                          Equation        ⁢                                  ⁢        6            
Solving Equation 6 for the new duty cycle Dnew yields,
                              D          new                =                                            V                              in                ⁢                                  -                                ⁢                old                                                    V                              in                ⁢                                  -                                ⁢                new                                              ·                      D            old                                              Equation        ⁢                                  ⁢        7            
The computations for the compensation condition described in Equation 7 consist of a division followed by a multiplication. Since the division is a more complex operation than a multiplication, in many cases it is preferable to perform the division by a look-up-table operation followed by an additional multiplication, as shown in Equation 8.
                              D          new                =                              1                          V                              in                ⁢                                  -                                ⁢                new                                              ·                      V                          in              ⁢                              -                            ⁢              old                                ·                      D            old                                              Equation        ⁢                                  ⁢        8            
U.S. Pat. No. 7,239,257 B1 discloses the use of a look-up-table for performing such a division.
In addition, U.S. Pat. No. 7,239,257 B1 discloses that when using a feedback unit with an integrator, such as the earlier described feedback unit in FIG. 3B, one of the multiplications can be avoided by using a nominal value of Vin-old=Vin-min, where Vin-min is the minimum measured input voltage. The look up table is then scaled with Vin-min.
The calculation of a compensated duty cycle therefore becomes:
                              D          new                =                                            V                              in                ⁢                                  -                                ⁢                min                                                    V                              in                ⁢                                  -                                ⁢                new                                              ·                      D            old                                              Equation        ⁢                                  ⁢        9            
Another way of addressing the problem of the computational requirements caused by the divisions is to make the delay in the digital pulse width modulator proportional to the reciprocal of the input voltage. This mixed signal solution is disclosed in X. Zhang and D. Maksimovic, □Digital PWM/PFM Controller with Input Voltage Feed-Forward for Synchronous Buck Converters□, in Proc. IEEE Appl. Power Electron. Conf. Expo., February 2008, pp 523-528.
A problem experienced by known SMPS controllers, that use a feedback unit cascaded with a VFF compensator, is that the calculation of the compensation signal after the calculation of a duty cycle control signal by the feedback unit results in long computation times.
Moreover, the complex and time consuming division operation with an additional multiplication has to be performed every switch period even when the input voltage is stable.
Furthermore, a problem with known digital VFF compensators is that when the input voltage is located near a quantization level of the ADC for the input voltage, measurement noise will sometimes cause the quantized version of the input signal to change. The VFF compensation will then introduce transients on the output voltage even when the input voltage is nearly constant.
Due to the above-identified computational requirements, known systems use a digital signal processor (DSP) to calculate a compensated duty cycle. However, DSPs are expensive, have a high power-consumption and long computation times. DSPs are also large and not suitable for use in compact applications.
Known controllers for an SMPS are therefore inappropriate for applications that require a compact digital control unit in which power-consumption, cost restraints and computation times should be minimized.